}
if ( iommu_enabled )
- msi_msg_read_remap_rte(entry, msg);
+ iommu_read_msi_from_ire(entry, msg);
}
static int set_vector_msi(struct msi_desc *entry)
update_intremap_entry_from_msi_msg(iommu, pdev, msg);
}
+unsigned int amd_iommu_read_ioapic_from_ire(
+ unsigned int apic, unsigned int reg)
+{
+ *IO_APIC_BASE(apic) = reg;
+ return *(IO_APIC_BASE(apic)+4);
+}
+
+void amd_iommu_read_msi_from_ire(
+ struct msi_desc *msi_desc, struct msi_msg *msg)
+{
+}
+
int __init deallocate_intremap_table(void)
{
if ( int_remap_table )
.get_device_group_id = amd_iommu_group_id,
.update_ire_from_apic = amd_iommu_ioapic_update_ire,
.update_ire_from_msi = amd_iommu_msi_msg_update_ire,
+ .read_apic_from_ire = amd_iommu_read_ioapic_from_ire,
+ .read_msi_from_ire = amd_iommu_read_msi_from_ire,
};
{
int rc = -ENODEV;
- if ( !iommu_enabled )
- goto out;
-
rc = iommu_hardware_setup();
iommu_enabled = (rc == 0);
- out:
if ( force_iommu && !iommu_enabled )
panic("IOMMU setup failed, crash Xen for security purpose!\n");
struct iommu_ops *ops = iommu_get_ops();
ops->update_ire_from_msi(msi_desc, msg);
}
+
+void iommu_read_msi_from_ire(
+ struct msi_desc *msi_desc, struct msi_msg *msg)
+{
+ struct iommu_ops *ops = iommu_get_ops();
+ ops->read_msi_from_ire(msi_desc, msg);
+}
+
+unsigned int iommu_read_apic_from_ire(unsigned int apic, unsigned int reg)
+{
+ struct iommu_ops *ops = iommu_get_ops();
+ return ops->read_apic_from_ire(apic, reg);
+}
+
/*
* Local variables:
* mode: C
.get_device_group_id = intel_iommu_group_id,
.update_ire_from_apic = io_apic_write_remap_rte,
.update_ire_from_msi = msi_msg_write_remap_rte,
+ .read_apic_from_ire = io_apic_read_remap_rte,
+ .read_msi_from_ire = msi_msg_read_remap_rte,
};
/*
unsigned int apic, unsigned int reg, unsigned int value);
void amd_iommu_msi_msg_update_ire(
struct msi_desc *msi_desc, struct msi_msg *msg);
+void amd_iommu_read_msi_from_ire(
+ struct msi_desc *msi_desc, struct msi_msg *msg);
+unsigned int amd_iommu_read_ioapic_from_ire(
+ unsigned int apic, unsigned int reg);
static inline u32 get_field_from_reg_u32(u32 reg_value, u32 mask, u32 shift)
{
static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
{
if (ioapic_reg_remapped(reg))
- return io_apic_read_remap_rte(apic, reg);
+ return iommu_read_apic_from_ire(apic, reg);
*IO_APIC_BASE(apic) = reg;
return *(IO_APIC_BASE(apic)+4);
}
int (*get_device_group_id)(u8 bus, u8 devfn);
void (*update_ire_from_apic)(unsigned int apic, unsigned int reg, unsigned int value);
void (*update_ire_from_msi)(struct msi_desc *msi_desc, struct msi_msg *msg);
+ void (*read_msi_from_ire)(struct msi_desc *msi_desc, struct msi_msg *msg);
+ unsigned int (*read_apic_from_ire)(unsigned int apic, unsigned int reg);
};
void iommu_update_ire_from_apic(unsigned int apic, unsigned int reg, unsigned int value);
void iommu_update_ire_from_msi(struct msi_desc *msi_desc, struct msi_msg *msg);
+void iommu_read_msi_from_ire(struct msi_desc *msi_desc, struct msi_msg *msg);
+unsigned int iommu_read_apic_from_ire(unsigned int apic, unsigned int reg);
void iommu_suspend(void);
void iommu_resume(void);